Signal Assignment
A sequential or concurrent statement which creates events on a signal.
Syntax
[Label:] {see Rules}
Target <= [Options] Expression [after TimeExpression],
Expression [after TimeExpression],
... ;
Target = {either} SignalName Aggregate
Options = {either}
guarded {must be in a guarded block}
transport
reject TimeExpression inertial
Where
architecture-begin--end
block-begin--end
generate-begin--end
See Sequential Statement
Rules
Sequential statements can be labelled in VHDL'93, but not in VHDL'87.
The default delay mode (inertial) means that pulses shorter than the delay (or
the reject period if specified) are ignored. Transport means that the
assignment acts as a pure delay line.
All delays are relative to the time when the assignment executes.
A signal assignment with no delay or zero delay will cause an event after a
delta delay, which means that the event happens only when all of the
currently active processes have finished executing (i.e. after one simulation
cycle).
A process containing one or more assignments to a signal has a driver for
that signal.
For a signal with multiple drivers, the values of all the drivers are passed to
the resolution function which calculates the value of the signal.
Assigning the value null to a guarded signal disconnects the driver from the
resolution function.
A guarded assignment only executes when the guard expression at the top of
the surrounding block is true.
Things to remember
A signal assignment does not immediately change the value of the signal;
there is always a delay of at least one delta.
Synthesis
Delays are ignored for synthesis; use tool specific timing constraints instead.
The Expression on the right hand side is synthesized as combinational logic.
The Target is synthesized as a connection in a combinational processes, as a
transparent latch when incompletely assigned in a combinational process, or
as a register in a clocked process.
Tips
Multiple events can be created by one signal assignment to define test
vectors (see last example below), but it is better to use several simple signal
assignments separated by wait for statements (see Wait).
Simulation speed is dependent on the number of signal assignments
executed. To speed up simulation, use fewer signals (which often means
fewer processes and more variables), and use integer or enumeration types
instead of arrays.
Example
A <= B;
A <= B nand C;
A <= B nand C after 0.2 NS;
(Cout, Sum) <= T'(A + B + Cin);
H <= "00", "01" after 10 NS, "10" after 20 NS;
See Also
Signal, Aggregate, Expression, Block, Conditional Assignment, Select,
Disconnect, Variable Assignment
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